DocumentCode
2356400
Title
Chip level power supply partitioning for IDDQ testing using built-in current sensors
Author
Prasad, Abhijit ; Walker, D.M.H.
Author_Institution
Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
fYear
2003
fDate
3-5 Nov. 2003
Firstpage
140
Lastpage
147
Abstract
The International Technology Roadmap for Semiconductors projects that IDDQ levels will rise rapidly with each technology node. In addition, manufacturing variations in the IDDQ level will be difficult to control. This combination will make it increasingly difficult to distinguish defect-free from defective chips via IDDQ tests. Built-in current sensors (BICSs) have been proposed to increase test resolution by virtually partitioning the supply mesh, so that each partition has a relatively small defect-free IDDQ level. In the future, such a scheme would require 100000 or more BICSs and thus the partitioning task needs to be automated. This paper presents a practical methodology to carry out this power supply partitioning.
Keywords
electric current measurement; integrated circuit design; integrated circuit testing; leakage currents; BICS; IDDQ level manufacturing variations; IDDQ testing; MOSFET leakage current; built-in current sensors; chip level power supply partitioning; supply mesh virtual partitioning; test resolution; Computer science; Failure analysis; Leakage current; Life testing; MOSFET circuits; Power supplies; Semiconductor device manufacture; Silicon on insulator technology; Temperature; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 2003. Proceedings. 18th IEEE International Symposium on
ISSN
1550-5774
Print_ISBN
0-7695-2042-1
Type
conf
DOI
10.1109/DFTVS.2003.1250105
Filename
1250105
Link To Document