DocumentCode :
235654
Title :
Analysis of modes effect on signal/power integrity in finite cavity for chip and die level packaging based on a hybrid full wave method
Author :
Xin Chang ; Leung Tsang
Author_Institution :
Electr. Eng. Dept., Univ. of Washington, Seattle, WA, USA
fYear :
2014
fDate :
27-30 May 2014
Firstpage :
2200
Lastpage :
2206
Abstract :
Most of the via modeling methods assumed that only the TEM mode which is the fundamental mode can propagate due to the thickness of substrate being electrically small, and all the higher order waveguide modes and anisotropic modes decay rapidly along the radial direction thus they can be ignored. However, for high speed chip and die level packaging system, due to the interested frequency range is higher and higher, the high order modes can be excited. At the same time, since the size of via holes can be comparable to the size of cavity, the excited modes for the via-plane pair structures may also be different from the cavity modes. These modes effects do contribute to the interactions among adjacent vias and cavity. Ignoring the modes effects may lead to inaccurate network parameters prediction for signal and power integrity analysis. In this paper, we first applied a hybrid full wave method based on Foldy-Lax multiple scattering equations method to model dense via array and multiple vias sharing same antipad, e.g. the case of differential via pair, in finite cavity. Then we investigate the geometric parameters and parasitic modes effects on signal/power integrity. Numerical results comparisons with commercial full wave solver show the hybrid full wave method has great accuracy and efficiency for modeling multiple vertical vias in finite cavity. We also explain the physical roots of the modes effect in order to improve signal link path bandwidth due to the modes effects.
Keywords :
TEM cells; chip scale packaging; network parameters; vias; waveguides; Foldy-Lax multiple scattering equations method; TEM mode; anisotropic modes; commercial full wave solver; dense via array; die level packaging system; excited modes; finite cavity mode; frequency range; fundamental mode; geometric parameters; high speed chip packaging system; higher order waveguide modes; hybrid full wave method; modeling methods; modes effect analysis; multiple vertical vias; network parameters prediction; parasitic modes effects; radial direction; signal link path bandwidth improvement; signal-power integrity; substrate thickness; via holes size; via-plane pair structures; Arrays; Cavity resonators; Equations; Method of moments; Packaging; Scattering; Transmission line matrix methods;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th
Conference_Location :
Orlando, FL
Type :
conf
DOI :
10.1109/ECTC.2014.6897608
Filename :
6897608
Link To Document :
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