DocumentCode :
2356569
Title :
A design methodology for the minimum die area of power MOSFET´s considering thermal resistance of the package
Author :
Il-Jung Km ; Hwang, Seong-Kyu ; Choi, Yeam-Ik ; Han, Min-Koo
Author_Institution :
Seoul Nat´´l Univ.
fYear :
1992
fDate :
1992
Firstpage :
202
Lastpage :
205
Keywords :
Ambient intelligence; Design methodology; Electric resistance; Electronic packaging thermal management; Geometry; MOSFET circuits; Shape; Solid modeling; Temperature; Thermal resistance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Power Semiconductor Devices and ICs, 1992. ISPSD '92. Proceedings of the 4th International Symposium on
Type :
conf
DOI :
10.1109/ISPSD.1992.991265
Filename :
991265
Link To Document :
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