Clockless Stochastic Decoding of Low-Density Parity-Check Codes

This paper introduces clock less stochastic decoding for high-throughput low-density parity-check (LDPC) decoders. Stochastic computation provides ultra-low-complexity hardware using simple logic gates. Clock less decoding eliminates global clocking, which eases the worst-case timing restrictions of synchronous stochastic decoders. The lack of synchronization might use outdated bits to update outputs in computation nodes, however, it does not significantly affect output probabilities. A timing model of clock less-computation behaviours under a 90nm CMOS technology is used to simulate the BER performance of the proposed decoding scheme. Based on our models, the proposed decoding scheme significantly reduces error floors due to the "lock-up", problem and achieves superior BER performance compared with conventional synchronous stochastic decoders.