DocumentCode :
2356786
Title :
Design and VLSI implementation of real-time weighted median filters
Author :
Chen, Chun Te ; Chen, Liang Gee ; Chiueh, Tzi-Dar ; Hsiao, Jue-Hsuan
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fYear :
1994
fDate :
5-8 Dec 1994
Firstpage :
91
Lastpage :
96
Abstract :
In this paper, a novel design method and VLSI implementation of weighted median filters is presented. The weight parameters are incremented to minimize the mean square error of the input signal and desired signal when the sub-set of the image data is applied. The suboptimal(optimal) weight set is achieved after 71 training cycles for 5*5 window size under the MSE criteria. A two-level adder tree architecture with pipelined latches is proposed to find the weighted median output with versatile definition of weight. It requires only K iterations to find output, where K means the resolution of the input signal samples. The task interleaved processing is also adopted to improve the throughput. The final chip layout with pipelined latches for 5*5 window size is also given in this paper. This high-speed VLSI implementation of weighted median filter will meet the real-time application requirements
Keywords :
VLSI; adders; flip-flops; image enhancement; median filters; pipeline processing; real-time systems; MSE criteria; high-speed VLSI implementation; image data; mean square error; pipelined latches; real-time weighted median filters; task interleaved processing; training cycles; two-level adder tree architecture; weight parameters; Adaptive filters; Convergence; Design methodology; Hardware; Mean square error methods; Signal resolution; Smoothing methods; Tellurium; Throughput; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1994. APCCAS '94., 1994 IEEE Asia-Pacific Conference on
Conference_Location :
Taipei
Print_ISBN :
0-7803-2440-4
Type :
conf
DOI :
10.1109/APCCAS.1994.514530
Filename :
514530
Link To Document :
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