Reducing test power, time and data volume in SoC testing using selective trigger scan architecture

Time, power and data volume are among the most challenging problems in test of system-on-chip (SoC) devices. These problems become even more important in scan-based test. The selective trigger scan architecture introduced in this paper addresses these problems. This architecture reduces switching activity in the circuit-under-test (CUT) and increases the scan clock frequency. The format of data for this reduced activity architecture enables us to perform a good compression and further reduce the test time. Our experiments on ISCAS 85 and 89 benchmark circuits show the effectiveness of this architecture in improving SoC test in terms of power, time and data volume.