Field-programmable multi-chip module (FPMCM) for high-performance DSP accelerator

We have described our work on FPMCM-I which integrates multiple FPGA chips by MCM technology, significantly increasing the logic capacity, reducing power consumption and speeding up the chip-to-chip communication. In the second part of the paper, we have described our bit-serial datapath circuit designs and their advantages over bit-parallel circuits on FPGA implementation. We have given some circuit layout examples of 2D FIR filter and IDCT circuits which demonstrates the efficiency of bit-serial circuits in terms of logic resource utilization, routability, IO pin utilization and performance