Buffer and controller minimisation for time-constrained testing of system-on-chip

Test scheduling and test access mechanism (TAM) design are two important tasks in the development of a system-on-chip (SOC) test solution. Previous test scheduling techniques assume a dedicated designed TAM which has the advantage of high flexibility in the scheduling process. However hardware overhead is incurred for implementing the TAM and additional routing is required. In this paper, we propose a technique that makes use of the existing functional buses for the test data transportation inside the SOC. We have dealt with the test scheduling problem with this new assumption and developed a technique to minimise the test-controller and buffer size for a bus-based multi-core SOC. We have solved the problem by using a constraint logic programming (CLP) technique and demonstrated the efficiency of our approach by running experiments on benchmark designs.