Control constrained resource partitioning for complex SoCs [intra-chip wireless interconnects]

When moving into the billion-transistor era, the wired interconnects used in conventional SoC test control models are rather restricted in not only system performance, but also signal integrity and transmission with continued scaling of feature size. On the other hand, recent advances in silicon integrated circuit technology are making possible tiny low-cost transceivers to be integrated on chip. Based on the recent development in "radio-on-chip" technology, a new distributed multihop wireless test control network has been proposed. Under the multilevel tree structure, the system optimization is performed on control constrained resource partitioning and distribution. Several system design issues such as radio-frequency nodes placement, clustering and routing problems are studied, with the integrated resource distribution including not only the circuit blocks to perform testing, but also the on-chip radio-frequency nodes for intra-chip communication.