Title :
Power-constrained embedded memory BIST architecture
Author :
Fang, Bai Hong ; Nicolici, Nicola
Author_Institution :
Dept. of Electr. & Comput. Eng., McMaster Univ., Hamilton, Ont., Canada
Abstract :
A new flexible, hierarchical and distributed power-constrained embedded memory built-in self-test (BIST) architecture for complex and heterogeneous systems-on-a-chip (SOCs) is presented. The proposed architecture consists of a shared technology-independent BIST controller, low area and low power memory BIST wrappers and serial interconnect between them for low routing-overhead. Due to its flexibility, in addition to reducing routing complexity and achieving high test concurrency under power constraints, the presented solution can simultaneously support multiple test algorithms for heterogeneous memories, as well as embed custom test algorithms required for new memory faults.
Keywords :
built-in self test; integrated circuit interconnections; integrated circuit testing; integrated memory circuits; logic design; logic testing; low-power electronics; system-on-chip; BIST controller; built-in self-test; distributed power-constrained embedded memory; embedded memory BIST; heterogeneous SOC; low area BIST wrappers; low power wrappers; memory faults; power-constrained BIST architecture; routing complexity reduction; serial interconnects; systems-on-a-chip; test concurrency; Built-in self-test; Circuit testing; Computer architecture; Integrated circuit interconnections; Memory architecture; Packaging; Power system reliability; System testing; Thermal management; Very large scale integration;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2003. Proceedings. 18th IEEE International Symposium on
Print_ISBN :
0-7695-2042-1
DOI :
10.1109/DFTVS.2003.1250143
