DocumentCode
2357049
Title
A memory built-in self-repair for high defect densities based on error polarities
Author
Nicolaidis, M. ; Achouri, N. ; Anghel, L.
fYear
2003
fDate
3-5 Nov. 2003
Firstpage
459
Lastpage
466
Abstract
This paper presents the architecture of a new memory built-in self-repair approach targeting memories affected by high defect densities (several orders of magnitude higher than in current technologies). Such a repair scheme is suitable for building memories in nano-technologies, which are subject to very high defect densities. The new approach allows combining two defective units to create a fault-free unit. For making this combination possible, the approach analyses the polarities of the errors produced by the faulty units of the memory, and combines units producing the same error polarities. The combination is done by means of functions that mask the errors of a particular polarity.
Keywords
fault tolerance; integrated circuit design; integrated memory circuits; logic design; logic testing; nanoelectronics; BISR scheme; combined defective units; error masking; error polarities; fault tolerance; high defect density; memory built-in self-repair; nanotechnology memories; Buildings; Circuit faults; Costs; FETs; Fault tolerance; Fault tolerant systems; Laboratories; Manufacturing; Testing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 2003. Proceedings. 18th IEEE International Symposium on
ISSN
1550-5774
Print_ISBN
0-7695-2042-1
Type
conf
DOI
10.1109/DFTVS.2003.1250144
Filename
1250144
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