Using a CLC low-pass filter to reduce the consequences of aging in steady-state regime of DC-DC converters

This paper presents a filter that can be used in the design of DC-DC converters, in order to mitigate the pernicious effects of the electrolytic capacitor´s equivalent series resistance (ESR), in steady state regime. The aging of electrolytic capacitors, used for smoothing the output voltage manifests itself by the increase of their ESR, and as a consequence of that, the output voltage ripple becomes very large. In this manner, the study of solutions to this problem is a very important subject for converters designers in low and medium power range. This paper shows that the use of a CLC filter reduces significantly the output voltage ripple without increasing too much the converter size. A study about the additional filtering expenses, like the impact on converter size and cost will be presented. Several theoretical, simulated and experimental results are presented for a buck type DC-DC converter, with different output filters, operating in the continuous conduction mode (CCM)