A VLSI architecture of SMU for strongly connected Viterbi decoder

An implementation of the Viterbi algorithm (VA) can be divided into three basic units, the transition metric unit, the added-compare-select unit, and the survivor memory unit (SMU). In this paper, a decoding scheme of SMU for a strongly connected Viterbi decoder is presented. In practice, two approaches, viz., the register-exchange method and the trace-back method, are very useful for survivor memory management. The presented decoding scheme has the property which is suitable for VLSI design using the systolic architecture. Finally, the conclusions show that the drawbacks occurring in the conventional SMU coding scheme can be overcome when the trellis is strongly connected instead of the original trellis