A high speed Reed-Solomon codec chip using lookforward architecture

Reed-Solomon (RS) code is one of the most important error controlling codes in digital communications. It is especially powerful for multiple error correction, thus suitable for random and burst error correction. In this paper, we propose a lookforward architecture that can reduce the number of cycles in the longer pipeline stage, thus resulting in a more efficient use of the pipelined structure. We implemented a (255,239) RS codec chip using the lookforward architecture. Both the code length and error correcting capability of the codec chip are programmable. This chip consists of 310,000 transistors in 61 mm² area with a 0.8 μm SPDM CMOS technology