Roundoff noise minimization for recursion specified fully pipelining digital filters

In the VLSI digital signal processing, a good balance between the speed, the hardware efficiency and the computational stability may be required. In this paper, the roundoff minimization under a fixed recursion structure is discussed. The aim of this study is to optimize the finite word length effect under the specifications of the speed and the required hardware amount. First, the freedom in a fixed recursion structure has been identified using the state variable system model, while the recursion structure is not limited within the conventional one of the state-space filters. Next, the roundoff noise has been analyzed and has been formulated in which the freedom appears explicitly. Finally, the effect of the roundoff noise minimization is demonstrated in the lattice recursion structure case