Fine pitch low temperature rdl damascene process development for TSV integration

Author

Li, H.Y. ; Pang, X.F. ; Ong, L.G. ; Li, H.B. ; Lee, W.S. ; Khan, Navas ; Teo, K.H. ; Gao, S.

Author_Institution

Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), 11, Science Park Road, Science Park II, Singapore, 117685

fYear

2010

fDate

8-10 Dec. 2010

Firstpage

52

Lastpage

55

Abstract

3D integration by TSV approach is a very hot topic now as an enabling technology for 3D wafer-level packaging and 3D IC. Re-distribution layer (RDL) process becomes more critical on high volume Cu (TSV) wafer because of Cu thermal stress effect. Fine pitch low temperature RDL is required in 3D packaging and 3D IC integration. We develop fine pitch (5µm space/5µm width) single and dual damascene processes at 150°C for the RDL process in the TSV (diameter 50µm, depth 100µm straight via) process integration. Dielectric cracks for the different structures in TSV integration is overcome by the low temperature RDL process. The breakdown field of low temperature dielectrics SiO2 and Si3N4 are 11.64MV/cm and 5.64MV/cm, respectively.

Keywords

Copper; Dielectrics; Plasma temperature; Stacking; Temperature; Three dimensional displays; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics Packaging Technology Conference (EPTC), 2010 12th

Conference_Location

Singapore, Singapore

Print_ISBN

978-1-4244-8560-4

Electronic_ISBN

978-1-4244-8561-1

Type

conf

DOI

10.1109/EPTC.2010.5702604

Filename

5702604