Test Pattern Dependent FPGA Based System Architecture for JTAG Tests

Author

Ostendorff, Steffen ; Wuttke, Heinz-Dietrich ; Sachsse, J. ; Escobar, Jorge Hernán Meza

Author_Institution

Integrated Hard- & Software Syst. Group, Ilmenau Univ. of Technol., Ilmenau, Germany

fYear

2010

fDate

11-16 April 2010

Firstpage

99

Lastpage

104

Abstract

The paper describes a new approach to speed-up and improve boundary scan based testing, by assigning functionality to a layer concept implemented in programmable logic. The motivation is driven by the constantly increasing gap between available and testable functionality of printed circuit boards. The motivation, architecture and build process of the proposed test and validation system is presented. Furthermore one selected example and first results are given to indicate the advantage of the proposed concept.

Keywords

automatic test pattern generation; boundary scan testing; field programmable gate arrays; logic testing; printed circuit testing; programmable logic devices; JTAG tests; boundary scan based testing; printed circuit boards testable functionality; programmable logic; test pattern dependent FPGA based system architecture; validation system; Circuit testing; Electronic equipment testing; Field programmable gate arrays; Hardware; Logic testing; Printed circuits; Programmable logic arrays; Programmable logic devices; Software testing; System testing; adaptive systems; automatic test equipment; boundary scan testing; field programmable gate arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

Systems (ICONS), 2010 Fifth International Conference on

Conference_Location

Menuires

Print_ISBN

978-1-4244-6231-5

Type

conf

DOI

10.1109/ICONS.2010.25

Filename

5464136