DocumentCode
2357382
Title
A VLSI circuit extractor with a parallel algorithm
Author
Yoon, Kwang S. ; Lee, Doo-Bok ; Rhee, Phill K. ; Han, Seok W. ; Park, Sung J.
Author_Institution
Dept. of Electron. Eng., Inha Univ., Inchon, South Korea
fYear
1994
fDate
5-8 Dec 1994
Firstpage
306
Lastpage
310
Abstract
This paper describes a parallel algorithm of an automated CMOS circuit extraction that transforms an IC layout into a circuit netlist suitable for circuit simulations. Using reconfigurable parallel machine architecture, the newly developed algorithm achieved a circuit extraction performance which is a constant time complexity. The layout of a CMOS inverter used successfully to demonstrate an efficiency of the newly developed algorithm
Keywords
CMOS integrated circuits; VLSI; circuit analysis computing; circuit layout CAD; integrated circuit layout; parallel algorithms; CMOS inverter layout; IC layout; VLSI circuit extractor; automated CMOS circuit extraction; circuit netlist; circuit simulation; parallel algorithm; reconfigurable parallel machine architecture; Circuits; Computational Intelligence Society; Hafnium; MOS devices; Parallel algorithms; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1994. APCCAS '94., 1994 IEEE Asia-Pacific Conference on
Conference_Location
Taipei
Print_ISBN
0-7803-2440-4
Type
conf
DOI
10.1109/APCCAS.1994.514567
Filename
514567
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