Electrical performance evaluation & comparison of high-speed multiple-chip 3D packages

With the increasing function integration, there is constant demand for multiple-chip packages with faster data rate in smaller footprint, therefore, 3D package technologies have attracted more and more attentions. In this paper, three common 3D packaging technologies are evaluated and compared in term of electrical performance, including the wire-bonding stacked-die package, the package on package, and the TSV stacked-die package, through frequency-domain electromagnetic analysis and time-domain circuit simulation when applied to DDR3 memory device as benchmark.