Electrical characterization, modeling and reliability analysis of a via last TSV

In this paper we will report on full wafer electrical characterization based on resistance of various lengths of daisy chain ranging from 10 to 100 TSV´s. The resistance of single TSV including metal contact is in range from 5~20 mOhms. Thermo-mechanical model was developed to investigate the impact of processing and temperature cycling on the mechanical and delamination stresses induced in the structure. The model showed that the thermal and delamination stresses are very much dependent on the conformality of the dielectric layer. For our specific via geometry it is simulated that 75MPa is the minimum adhesion strength required to avoid delamination. After the electrical measurement, the wafers were subjected to thermal cycling from -40 to 125°C for up to 1000 cycles. Wafers were electrically yielding after the 1000 cycles with limited yield loss. The paper reports on the root causes contributing to the decrease in electrical resistance and it was identified that damage to the probing pads is one of the main cause of failure.