DocumentCode
2357487
Title
A very fast three-mode retiming PLL with low jitter and wide operating margin
Author
Shirahama, Hirokatsu ; Taniguchi, Kenji ; Tsukahara, Osamu
Author_Institution
Kyushu Univ., Fukuoka, Japan
fYear
1994
fDate
5-8 Dec 1994
Firstpage
340
Lastpage
345
Abstract
The proposed PLL realizes a fast and wide-ranging pull-in, and a stable locked condition by controlling a frequency difference detector and a PLL core with a dual loop constants in three modes. Simulations of the PLL designed with an 0.8 μm bipolar devices and experiments using a PLL-IC together with PLAs demonstrated the features; a short pull-in time comparable to SAW filters even for 63 bit PRBS NRZ inputs, low output jitter and no slowly-recovering phase error
Keywords
bipolar digital integrated circuits; digital phase locked loops; jitter; timing circuits; 0.8 micron; 63 bit; PLAs; PLL-IC; PRBS NRZ signals; bipolar devices; dual loop constants; frequency difference detector; jitter; operating margin; phase error; pull-in time; simulation; three-mode retiming PLL; Bipolar integrated circuits; Clocks; Damping; Detectors; Frequency; Jitter; Optical signal processing; Phase locked loops; SAW filters; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1994. APCCAS '94., 1994 IEEE Asia-Pacific Conference on
Conference_Location
Taipei
Print_ISBN
0-7803-2440-4
Type
conf
DOI
10.1109/APCCAS.1994.514573
Filename
514573
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