Simplified process solution for a 150µm bump pitch flip chip packaging using C40 ULK wafer

This paper presents a simplified flip chip front-of-line process flow by means of eliminating de-flux and plasma processes as well as replacing the solder on pad (SOP) on solder mask defined (SMD) substrate design for a 150μm bump pitch flip chip packaging using C40 ULK (ultra low-K) wafer. Wafer sawing was performed with the combination of laser grooving and mechanical diamond blade dicing to prevent metal peeling problems which cannot be addressed by standard blade dicing process alone. In order to prevent the adherence of debris on the wafer active surface and the bumps during laser grooving, a water soluble protective coating material was coated on the wafer prior to laser grooving. An optimization was done in order to ensure that the bumps are fully covered and protected with the coating material. After the wafer preparation, three different front-of-line process approaches were conducted. The first approach is the standard flow which is the typical flip chip process involving flip chip attach, solder bump reflow, de-flux, prebake, plasma and underfill processes using a SOP on SMD substrate design and a clean type flux material. The second approach is a simplification of the standard flow in which the de-flux and plasma processes were removed. This approach uses a non-solder mask defined (NSMD) substrate design with organic solderability preservative (OSP) bump pad finishing in combination with a non-clean type flux material. Third approach, an alternate flow, is similar to the first and second approaches but utilizes Cu Pillar bumps in combination with SOP on SMD substrate and a clean type flux material, and with a NSMD with OSP substrate and a non-clean type flux respectively. The three (3) different approaches were evaluated and compared by assessing process risks of bump cracks/voids, non-wetting bumps and underfill voids through die shear test, cross-section, scanning acoustic microscopy (C-SAM) inspections. Moisture sensitivity level 3 (MSL3), 50x- - thermal cycle (TC 50x) and 20x reflow were conducted to assess package level reliability. Processibility and reliability results showed positive and comparable results for all the three approaches and demonstrated that a simplified solution can be achieved by using a NSMD substrate design with OSP and a non-clean type flux material.