DocumentCode
2357622
Title
Analysis and modeling of systematic and defect related yield issues during early development of a new technology
Author
Guldi, R. ; Watts, J. ; PapaRao, S. ; Catlett, D. ; Montgomery, J. ; Saeki, T.
Author_Institution
Texas Instrum. Inc., Dallas, TX, USA
fYear
1998
fDate
23-25 Sep 1998
Firstpage
7
Lastpage
12
Abstract
In every generation of new technology development, yield management engineers face new challenges in the detection and modeling of physical defects and systematic yield inhibitors. This paper discusses several approaches to yield modeling that were useful during initial development of 64M DRAM technology. These approaches combined electrical source defect analysis (ESDA) supplemented by end-of-line failure analysis (FA) with in-line defect monitoring using sensitive inspection recipes at frequent processing steps to identify and track the systematic yield and particle issues that must be overcome
Keywords
DRAM chips; failure analysis; fault location; inspection; integrated circuit design; integrated circuit reliability; integrated circuit yield; process monitoring; semiconductor process modelling; surface contamination; DRAM technology; defect related yield issues; early technology development; electrical source defect analysis; end-of-line failure analysis; frequent processing steps; in-line defect monitoring; inspection recipes; modeling; particle issues; physical defects; systematic yield inhibitors; systematic yield issues; technology development; yield management; yield modeling; Circuit testing; Engineering management; Face detection; Failure analysis; Inhibitors; Inspection; Instruments; Printing; Random access memory; Technology management;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Semiconductor Manufacturing Conference and Workshop, 1998. 1998 IEEE/SEMI
Conference_Location
Boston, MA
ISSN
1078-8743
Print_ISBN
0-7803-4380-8
Type
conf
DOI
10.1109/ASMC.1998.731371
Filename
731371
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