Title :
Low cost and high performance p-doped triple-gate access transistor for embedded DRAM memory cell
Author :
Berthollet, F. ; Cremer, S. ; Bossu, G. ; Carrère, J.P. ; Jeanjean, D. ; Pinzelli, L. ; Pantel, R. ; Lalanne, F. ; Plossu, C. ; Poncet, A.
Author_Institution :
Crolles R&D Center, STMicroelectronics, Crolles, France
Abstract :
A new triple-gate transistor, formed by recessing the oxide layer in the isolation trenches, without any other significant modification in the conventional planar transistor process flow, is evaluated as the access transistor of the 65 nm node embedded DRAM (eDRAM) memory cell. In addition to the own advantages of this structure (high on-state current (Ion), small Body Bias Effect (BBE), excellent short channel effects (SCE) immunity), this transistor shows a lower off-state current (Ioff) and better mismatch characteristics than the conventional planar one, thanks to the adoption of a p-doped gate electrode.
Keywords :
DRAM chips; etching; field effect memory circuits; field effect transistors; isolation technology; semiconductor doping; body bias effect; eDRAM memory cell; embedded DRAM memory cell; etching; isolation trench; mismatch characteristics; p-doped triple-gate access transistor; planar transistor process; short channel effects; Capacitors; Costs; Doping; Electric variables; Electrodes; Etching; Fabrication; Immune system; Random access memory; Research and development;
Conference_Titel :
Solid State Device Research Conference, 2009. ESSDERC '09. Proceedings of the European
Conference_Location :
Athens
Print_ISBN :
978-1-4244-4351-2
Electronic_ISBN :
1930-8876
DOI :
10.1109/ESSDERC.2009.5331317
