DocumentCode
2357851
Title
A model for robust electrostatic design of nanowire FETs with arbitrary polygonal cross sections
Author
De Michielis, Luca ; Selmi, Luca ; Ionescu, A.M.
Author_Institution
Nanolectronic Devices Lab., Swiss Fed. Inst. of Technol. Lausanne, Lausanne, Switzerland
fYear
2009
fDate
14-18 Sept. 2009
Firstpage
472
Lastpage
475
Abstract
In this work a quasi-analytical physical model for the accurate prediction of the potential of GAA nanowire transistors with an arbitrary regular polygon as a cross section is developed. Two case studies concerning triangular and square cross-sections are particularly investigated and analyzed. The model is then extended to the transport direction; general expressions for the natural length are derived and validated by means of two- and three-dimensional numerical device simulations. Basic design guidelines, using an original analytical expression of the natural length, for robust electrostatic design are proposed, to predict the minimum technological gate length able to assure immunity to the SCEs.
Keywords
MOSFET; electrostatics; nanoelectronics; nanowires; semiconductor device models; semiconductor quantum wires; 2D numerical device simulations; 3D numerical simulations; GAA nanowire transistors; SCE immunity; arbitrary polygonal cross sections; gate all around MOSFET; minimum technological gate length; nanowire FET model; natural length analytical expression; quasianalytical physical model; robust electrostatic design; Electrostatics; FETs; Genetic expression; Guidelines; Laboratories; MOSFETs; Nanoscale devices; Numerical simulation; Predictive models; Robustness;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Device Research Conference, 2009. ESSDERC '09. Proceedings of the European
Conference_Location
Athens
ISSN
1930-8876
Print_ISBN
978-1-4244-4351-2
Electronic_ISBN
1930-8876
Type
conf
DOI
10.1109/ESSDERC.2009.5331322
Filename
5331322
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