Drain / substrate coupling impact on DIBL of Ultra Thin Body and BOX SOI MOSFETs with undoped channel

For ultimate MOSFET scaling, ultra thin body and BOX SOI transistors have become of great interest, as they are known to dramatically reduce short channel effects (SCE) while maintaining very high device performance. In this work, we emphasize the impact of the substrate / BOX interface space charge conditions on the drain induced barrier lowering (DIBL) increase with gate length reduction, as this drastically changes the channel position in the film and the drain coupling with the channel via substrate and through the BOX. Several modifications to the MASTAR DIBL model are proposed based on ATLAS simulations of the studied structures, in order to explain those effects and fit the experimental data.