Title :
A proposed DDT/IDCT chip design using quaternary logic
Author_Institution :
Dept. of Electr. Eng., California Univ., Davis, CA, USA
Abstract :
CMOS quaternary threshold logic circuits are used in the design of the instruction memory and arithmetic sections of a proposed single-chip implementation of a unified discrete cosine transform/inverse discrete cosine transform (DCT/IDCT) architecture. The chip is projected to be capable of real-time processing of 10-MHz video signals. The unified DCT/IDCT architecture is described, and the use of quaternary logic circuits is discussed. A 17.5% area savings has been achieved.<>
Keywords :
CMOS integrated circuits; many-valued logics; microprocessor chips; signal processing; video signals; 10 MHz; 10-MHz video signals; DDT/IDCT chip design; arithmetic sections; discrete cosine transform; instruction memory; inverse discrete cosine transform; quaternary logic; real-time processing; Arithmetic; CMOS logic circuits; CMOS memory circuits; Chip scale packaging; Data compression; Discrete cosine transforms; Logic circuits; Logic design; Signal processing; Video compression;
Conference_Titel :
Multiple-Valued Logic, 1988., Proceedings of the Eighteenth International Symposium on
Conference_Location :
Palma de Mallorca, Spain
Print_ISBN :
0-8186-0859-5
DOI :
10.1109/ISMVL.1988.5146
