Title :
An experimental study of temperature influence on electrical characteristics of ferroelectric P(VDF-TrFE) FETs on SOI
Author :
Salvatore, Giovanni A. ; Lattanzio, Livio ; Bouvet, Didier ; Ionescu, Adrian M.
Author_Institution :
Ecole Polytech. Fed. de Lausanne, Lausanne, Switzerland
Abstract :
We report on the fabrication and electrical characterization of ferroelectric FETs (Fe-FET) on fully depleted SOI. The transistor gate stack is made by a 45 nm P(VDF-TrFE) 70%-30% layer on top of 10 nm thermal SiO2. The improved junction leakage control in thin SOI enables the accurate investigation of the electrical DC characteristics of Fe-FETs in a range of temperature from 25degC up to 90degC. Reductions of the non-saturated hysteretic loop and of Ion/Ioff are observed at high temperature but the Fe-FET remarkably maintains basic switch functionality with Ion/Ioff> 105 up to 85degC. We particularly report and explain the parabolic dependence of the SOI Fe-FET subthreshold swing, SS, on the temperature, featuring an experimental minimum.
Keywords :
ferroelectric devices; ferroelectric materials; ferroelectric switching; ferroelectric thin films; hysteresis; leakage currents; organic field effect transistors; polymer blends; polymer films; silicon compounds; silicon-on-insulator; FeFET device; Si; SiO2; electrical DC characteristics; ferroelectric P(VDF-TrFE) FET; fully depleted SOI; hysteretic loop; junction leakage; size 10 nm; size 45 nm; subthreshold swing; switch functionality; temperature 25 degC to 90 degC; transistor gate stack; Dielectric substrates; Electric variables; FETs; Ferroelectric materials; Hysteresis; MOSFETs; Silicon; Switches; Temperature dependence; Temperature distribution;
Conference_Titel :
Solid State Device Research Conference, 2009. ESSDERC '09. Proceedings of the European
Conference_Location :
Athens
Print_ISBN :
978-1-4244-4351-2
Electronic_ISBN :
1930-8876
DOI :
10.1109/ESSDERC.2009.5331330
