An experimental study of temperature influence on electrical characteristics of ferroelectric P(VDF-TrFE) FETs on SOI

We report on the fabrication and electrical characterization of ferroelectric FETs (Fe-FET) on fully depleted SOI. The transistor gate stack is made by a 45 nm P(VDF-TrFE) 70%-30% layer on top of 10 nm thermal SiO₂. The improved junction leakage control in thin SOI enables the accurate investigation of the electrical DC characteristics of Fe-FETs in a range of temperature from 25degC up to 90degC. Reductions of the non-saturated hysteretic loop and of I_on/I_off are observed at high temperature but the Fe-FET remarkably maintains basic switch functionality with I_on/I_off> 10⁵ up to 85degC. We particularly report and explain the parabolic dependence of the SOI Fe-FET subthreshold swing, SS, on the temperature, featuring an experimental minimum.