Title :
Selection of rare earth silicate with SrO capping for EOT scaling below 0.5 nm
Author :
Kakushima, K. ; Okamoto, K. ; Koyanagi, T. ; Tachi, K. ; Kouda, M. ; Kawanago, T. ; Song, J. ; Ahmet, P. ; Tsutsui, K. ; Sugii, N. ; Hattori, T. ; Iwai, H.
Author_Institution :
Interdiscipl. Grad. Sch. of Sci. & Eng., Tokyo Inst. of Technol., Yokohama, Japan
Abstract :
An aggressive EOT scaling with high-k gate dielectrics has been presented by selection of a rare earth silicate (La, Ce and Pr) as an interfacial layer with La2O3 stacking. Among silicates, La2O3/Ce-silicate nFET has performed a small EOT of 0.51 nm with a reduced gate leakage current of 102 A/cm2. SrO capping further reduces the gate leakage current also with a smaller EOT with improved subthreshold slope. A guideline for EOT scaling using RE-silicate in combination with SrO capping is proposed.
Keywords :
cerium compounds; field effect transistors; lanthanum; leakage currents; praseodymium compounds; strontium compounds; CeSiO-La2O3; LaSiO-La2O3; PrSiO-La2O3; SrO; aggressive EOT scaling; equivalent oxide thickness; gate leakage current; high-k gate dielectrics; interfacial layer; nFET; rare earth silicate; size 0.51 nm; stacking; subthreshold slope; Annealing; Dielectric constant; Geoscience; High K dielectric materials; High-K gate dielectrics; Inorganic materials; Leakage current; Silicon; Stacking; Temperature;
Conference_Titel :
Solid State Device Research Conference, 2009. ESSDERC '09. Proceedings of the European
Conference_Location :
Athens
Print_ISBN :
978-1-4244-4351-2
Electronic_ISBN :
1930-8876
DOI :
10.1109/ESSDERC.2009.5331331
