Title :
A practical all-path timing-driven place and route design system
Author :
Chang, Chwen-Cher ; Lee, James ; Stabenfeldt, Mike ; Tsay, Ren-Song
Author_Institution :
ArcSys Inc., Sunnyvale, CA, USA
Abstract :
We have developed a practical timing-driven design system that achieves 17% cycle time improvement with only up to 32% run time penalty, and as low as 1% area overhead in real, 5000-7000-cell designs. This system is based on a Slack Graph concept that efficiently and effectively represents all-path timing constraints and allows optimal trade-off between timing and die size
Keywords :
circuit layout CAD; integrated circuit layout; network routing; timing; all-path timing constraints; place/route design system; slack graph concept; timing-driven design system; Costs; Delay effects; Design methodology; Foundries; Multimedia communication; Multimedia computing; Routing; Semiconductor device measurement; Timing; Wireless communication;
Conference_Titel :
Circuits and Systems, 1994. APCCAS '94., 1994 IEEE Asia-Pacific Conference on
Conference_Location :
Taipei
Print_ISBN :
0-7803-2440-4
DOI :
10.1109/APCCAS.1994.514612
