Effects of stress in polysilicon VIA - first TSV technology

Through Silicon Via (TSV) is a very attractive solution for 3D stacking. One of the main concerns regarding the TSV technologies is the resulting stress build up inside the silicon substrate that induces warpage or expansion at the wafer level, crystalline defects in the neighboring silicon of the TSV and finally can impact performances and reliability of CMOS device as well. In this work, we show results on how the stress is built up in the substrate during the fabrication of via-first polysilicon TSVs and the influence of some of the specific process steps. Then, simulated data will be presented and compared to experimental findings. Then, stress release during back side processing is demonstrated by wafer expansion and cracks of the thinned wafer depending on the glue material used. We also present characterizations of silicon defects by chemical revelation around the TSV structures after back side processing. The impact of thin wafer expansion on TSV electrical performances will be then presented. Finally we show that with the optimization of some key process steps, stress induced in polysilicon via-first technology may be acceptable for IC integration.