Author :
Mitard, J. ; Martens, K. ; DeJaeger, B. ; Franco, J. ; Shea, C. ; Plourde, C. ; Leys, F.E. ; Loo, R. ; Hellings, G. ; Eneman, G. ; Wang, Wei-E ; Lin, J.E. ; Kaczer, B. ; DeMeyer, K. ; Hoffmann, T. ; DeGendt, S. ; Caymax, M. ; Meuris, M. ; Heyns, M.M.
Abstract :
In this study, we report a direct comparison between two epitaxial silicon processes: 500degC using SiH4 and 350degC using Si3H8. Following four different metrics, we demonstrate that the reduction of silicon growth temperature results into the introduction of negatively charged defects possibly located at the Si/SiO2interface. However, the Epi Si growth at 350degC with Si3H8 remains beneficial compared to a growth performed at 500degC-SiH4 especially when thin EOT Ge pFETs are targeted.
Keywords :
elemental semiconductors; epitaxial growth; germanium; power field effect transistors; semiconductor growth; silicon; Ge; Ge-pFET performance; Si; SiH4; epi-Si growth temperature; epitaxial silicon processes; temperature 350 degC to 500 degC; Dielectrics and electrical insulation; High K dielectric materials; High-K gate dielectrics; III-V semiconductor materials; Inorganic materials; Interface states; Semiconductor films; Silicon; Temperature dependence; Temperature measurement;
