An innovative surrogate chip for accurate high-speed wire bond package measurement

Wire bond packaging for semiconductor devices has been the choice of low cost implementation to memory interface and high-speed transceivers. However, accurate characterization for wire bond package remains challenging owing to lack of consistent probing methodology. Meanwhile, semiconductor devices tend to have increasingly higher density of I/O, logic circuits and transceiver circuits yet shrinking die size. Therefore, the bonding die pads have to be allocated ever closer to accommodate more I/Os, transceivers and powers. This has made any 2-port transfer function measurement involving link between die pad through wire to BGA balls next to impossible. In this paper, an innovative measurement technology, surrogate chip substrate is proposed to enable accurate and consistent wire bond package measurements for multiple High Speed Serial Interface (HSSI) channel, Double Data Rate (DDR) interface, and wire bond implementation of Power Distribution Networks (PDN).