Propagation and diagnosis faulty LUTs in an FPGA

This paper proposes a new technique for propagation and diagnosis the faulty LUTs (Look Up Tables) in an FPGA (Field Programmable Gate Arrays) using a simple parallel in serial out shift register. The proposed fault propagation design helps in diagnosing the multiple faulty LUTs precisely by avoiding any fault masking. This method has been tested on the commercial FPGA and the experimental results are provided. The experimental result shows that time taken to test 4656 LUTs exhaustively is 196 seconds.