DocumentCode
2358822
Title
Efficient AFT implementation in FPGAs to detect potential electromigration failures
Author
Rayaprolu, SaiDeepa ; Vemuru, Srinivasa ; Niamat, Mohammed
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., Univ. of Toledo, Toledo, OH, USA
fYear
2012
fDate
6-8 May 2012
Firstpage
1
Lastpage
6
Abstract
An efficient and modular architecture is used to implement Arithmetic Fourier Transform algorithm as a Built-in-Self Test structure to identify electromigration faults in FPGAs. Xilinx Virtex 5 FPGA, implemented in 65 nm fabrication process, is used to implement BIST and simulate the electromigration failure mechanisms. Fault signatures are developed for different interconnect FPGA resources and simulation results are presented.
Keywords
Fourier transforms; built-in self test; electromigration; field programmable gate arrays; logic testing; BIST; FPGA; Xilinx Virtex 5; arithmetic fourier transform algorithm; built-in-self test structure; electromigration failures; electromigration faults; fault signatures; modular architecture; size 65 nm; Circuit faults; Field programmable gate arrays; Fourier transforms; Hardware; Integrated circuit interconnections; Integrated circuit modeling; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Electro/Information Technology (EIT), 2012 IEEE International Conference on
Conference_Location
Indianapolis, IN
ISSN
2154-0357
Print_ISBN
978-1-4673-0819-9
Type
conf
DOI
10.1109/EIT.2012.6220768
Filename
6220768
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