Stretching quasi delay insensitivity by means of extended isochronic forks

Handshake circuits can be mapped onto QDI circuits using generic standard-cells only. Despite several interesting optimizations, the resulting circuits are large. By extending the isochronic-fork assumption, we arrive at a class of asynchronous circuits that particularly allow efficient realizations of double-rail data paths. This paper defines the extended isochronic fork, discusses its implementation, and provides numerous examples. The impact on circuit costs is evaluated for a DCC error decoder. In an appendix a basic arbiter (mutual-exclusion element) is presented that requires simple CMOS gates only. We also propose a 3-way generalization of this arbiter