Factors affecting electromigration and current carrying capacity of FC and 3D IC interconnects

Electromigration (EM) failure in flip-chip bumps has emerged as a major reliability concern due to potential elimination of Pb from flip-chip bumps and a continuous drive to increased IO density resulting in a reduction of bump pitch and size. Additionally, the rapid development and implementation of 3D IC structures is introducing new interconnects (u-bumps, RDL, microvias, and TSVs) at a much finer geometries, raising concerns about electromigration and current carrying capacity of these interconnects. In order to estimate the current carrying capacity of these interconnect structures, electromigration tests need to be conducted. However, conducting an EM test is not a trivial task as factors such as test structure, resistance and joule heating measurement, and failure criteria have a direct impact on the estimated current carrying capacity. In addition, metallurgical features such as solder alloy used, UBM stackup and materials, and surface finish on the substrate side have a significant impact on EM reliability. This paper discusses some of the factors affecting the EM reliability of fine pitch interconnects and how test design, data collection and interconnect metallurgies affect the EM performance.