Systematic abstractions of microprocessor RTL models to enhance simulation efficiency

The steady persistence of Moore´s law over decades has lead to astronomical decrease in feature size supported by semiconductor manufacturing technology, which has increased the transistor count on a single chip. This has led to complex and advanced microprocessor microarchitectures and functionalities. Consequently, the need for efficient methodologies for microprocessor design has given rise to new challenges for hardware systems designers to address the ever growing concern over bridging the design-productivity gap and reduction of the time-to-market. An estimated 70% of the development cycle of a microprocessor is spent in validation, and in the absence of a standard and proven formal verification technology, simulation based validation occupies the major share of the validation cycle. Functional correctness of a microprocessor mostly refers to conformance of the microarchitecture implementation to the instruction set architecture (ISA). Through unit level, block level, full-chip level, and system level simulation the designer can check for such functional correctness. However, simulations for full-chip verification consume ample amount of time, directly affecting the design and eventually the time-to-market. Evidently, simulation efficiency is a major concern for most designers, and the development of methodologies to reduce simulation time is crucial. To address this concern we develop certain methodologies that leverage the idea of systematic abstractions on microarchitectures defined at the RTL level. We experiment with a PowerPC model written in SystemC and show results of 50% improvement in simulation efficiency.