DocumentCode :
2359947
Title :
Solder joint encapsulation and reliability using dippable underfill
Author :
Yeo, Yen Chen ; Huang, Mark ; Che, Fa Xing ; Chong, Ser Choong ; Lim, Keith Cheng Sing ; Thew, Serene ; Vasarla, Nagendra Sekhar ; Gao, Shan
Author_Institution :
Inst. of Microelectron., A*STAR (Agency for Sci., Technol. & Res.), Singapore, Singapore
fYear :
2010
fDate :
8-10 Dec. 2010
Firstpage :
710
Lastpage :
714
Abstract :
The demand for flip chip devices is rising to meet increasingly strict requirements for smaller package size, multiple-die stacking and higher interconnection densities. There are, however, two major issues facing the flip chip process, which are reliability impact by the stresses induced in the solder joints during reflow and high cost for underfill process and materials. Current alternatives to capillary underfill for Pb-free products such as wafer-level underfill and no-flow underfill introduce additional and low-yield process steps. The new dipping adhesive incorporates underfill in attach-and-reflow step and protects each Pb-free solder joint individually, thus enhancing joint reliability. The dippable underfill (DUF) has potential applications in fine-pitch and fine-gap chip-to-chip (C2C) and chip to wafer (C2W) stacked Pb-free packages, as conventional capillary underfill may not be able to achieve void-free underfilling due to the ultra-fine gap, for instance, less than 10μm. Cost reduction is also achieved because expensive capillary underfill material and equipment is not required anymore. Less material is used in solder joint encapsulation compared to fully-filled capillary underfill (CUF). Lastly, due to the reduction in the number of process steps, the process yield is improved while the process time is also reduced. This is especially important for high-volume production and can result in substantial cost savings. In addition, finite element analysis (FEA) was conducted to investigate the effect of dippable underfill on solder joint reliability. Simulation results showed that dippable underfill results in higher solder joint thermal fatigue life.
Keywords :
finite element analysis; flip-chip devices; integrated circuit interconnections; integrated circuit packaging; integrated circuit reliability; reflow soldering; solders; thermal management (packaging); attach-and-reflow step; capillary underfill equipment; capillary underfill material; chip-to-wafer stacked Pb-free package; cost reduction; dippable underfill; dipping adhesive; fine-gap chip-to-chip; fine-pitch chip-to-chip; finite element analysis; flip chip device; flip chip process; interconnection density; low-yield process; multiple-die stacking; no-flow underfill; package size; reflow soldering; solder joint encapsulation; solder joint reliability; solder joint thermal fatigue life; wafer-level underfill;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Packaging Technology Conference (EPTC), 2010 12th
Conference_Location :
Singapore
Print_ISBN :
978-1-4244-8560-4
Electronic_ISBN :
978-1-4244-8561-1
Type :
conf
DOI :
10.1109/EPTC.2010.5702730
Filename :
5702730
Link To Document :
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