DocumentCode
2360037
Title
A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach
Author
Panades, Ivan Miro ; Greiner, Alain ; Sheibanyrad, Abbas
Author_Institution
STMicroelcctronics, Grenoble
fYear
2006
fDate
Sept. 2006
Firstpage
1
Lastpage
5
Abstract
The paper presents the DSPIN micro-network, that is an evolution of the SPIN architecture. DSPIN is a scalable packet switching micro-network dedicated to GALS (globally asynchronous, locally synchronous) clustered, multi-processors, systems on chip. The DSPIN architecture has a very small footprint and provides to the system designer both guaranteed latency, and guaranteed throughput services for real-time applications
Keywords
multiprocessing systems; network-on-chip; DSPIN architecture; GALS; globally asynchronous locally synchronous multiprocessors; network-on-chip; system-on-chip; Clocks; Costs; Delay; Memory architecture; Network-on-a-chip; Packet switching; Quality of service; System-on-a-chip; Throughput; Time division multiplexing; Bi-synchronous FIFO; DSPIN; GALS; Globally Asynchronous Locally Synchronous; Mesochronous; Network on Chip; NoC; SPIN; SoC; System on Chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Nano-Networks and Workshops, 2006. NanoNet '06. 1st International Conference on
Conference_Location
Lausanne
Print_ISBN
1-4244-0391-X
Type
conf
DOI
10.1109/NANONET.2006.346219
Filename
4152802
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