DocumentCode :
2360038
Title :
Advanced QFN Surface Mount Application Notes development
Author :
Tseng, Andy ; Lin, Mark ; Hu, Bruce ; Chen, Jw ; Wan, Jm ; Lee, Sunny ; Lai, Yi-Shao
Author_Institution :
ASE (US), Inc., Sunnyvale, CA, USA
fYear :
2010
fDate :
8-10 Dec. 2010
Firstpage :
737
Lastpage :
742
Abstract :
The advanced Quad Flat No-Lead (aQFN) package is an enhanced version of conventional QFN with multiple row terminals of featuring higher number of I/O ports. The aQFN thermal and electrical performance are superior due to smaller profile and shorter interconnects and the solder wettability control and board-level thermo-mechanical reliability are greatly enhanced over conventional QFN because of the higher package standoff. aQFN provides similar I/O number approaching that of a BGA-type chip-scale package (FBGA) but much less cost since the expensive substrate is replaced by lead frame. aQFN turns out to be an ideal low cost solution for electrical components of portable telecommunication applications such as IrDA, blue-tooth, RFID, cell phone baseband etc. for its superior thermal, electrical, reliability performances and miniaturized package size, With such advantages, the replacement of FBGA with aQFN in low up to medium lead-count applications is therefore highly expectable, especially for handheld & PDA devices with its related applications. With such higher pin-count, multi-row and small terminal pitch than QFN, how to design the aQFN package terminals for printed circuit board layout and the stencil patterning and opening for solder paste printing become crucial issues. aQFN will be introduced in terms of its application advantages, development, fabrication process flow, SMT process with stencil design guideline for surface mount assembly yield. Finally, “Surface Mount Application Notes” have been issued.
Keywords :
ball grid arrays; chip scale packaging; circuit reliability; notebook computers; printed circuit layout; surface mount technology; BGA-type chip-scale package; FBGA; I/O ports; PDA devices; SMT process; aQFN package; advanced QFN surface mount application notes development; advanced quad flat no-lead package; board-level thermo-mechanical reliability; electrical performance; fabrication process flow; multiple row terminals; printed circuit board layout; solder wettability control; telecommunication applications; thermal performance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Packaging Technology Conference (EPTC), 2010 12th
Conference_Location :
Singapore
Print_ISBN :
978-1-4244-8560-4
Electronic_ISBN :
978-1-4244-8561-1
Type :
conf
DOI :
10.1109/EPTC.2010.5702735
Filename :
5702735
Link To Document :
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