The study of thermo-mechanical reliability for multi-layer stacked chip module with through-silicon-via (TSV)

Through-silicon-via (TSV) technology permits devices to be placed and wired in the third dimension. Currently, there is a strong motivation for the semiconductor industry to move to 3-D integration using the TSV approach due to many advantages of TSV application. However, there are also some challenges for stacked die package with TSVs. One of the challenges is thermo-mechanical reliability of multi-layer stacked chip modules when subjected to temperature cycling loading. In this paper, multi-layer stacked chip modules with 6 via-last memory chips and one via-middle logic chip were investigated in terms of thermo-mechanical reliability using finite element modeling and simulation method in the design stage for packaging material selection, solder joint layout design, package size effect on reliability, and solder joint fatigue life assessment and so on. The simulation results show that underfill is one of the most important parameters relating to solder joint thermal fatigue life. The effect of underfill glass transition temperature (T_g) and coefficient of thermal expansion (CTE) on solder joint life is significant. High T_g and low CTE underfill results in high solder joint life. Substrate CTE is another key parameter in terms of solder joint thermo-mechanical reliability. When underfill with low T_g is used in package, package with low CTE substrate results in high solder joint life. However, when high T_g underfill is used in package, the effect of substrate CTE on solder joint is not significant. In addition, the effects of following parameters on solder joint reliability have also been investigated: solder joint layout design of peripheral vs. full array, solder joint alloy (low Ag vs. high Ag content solder), mold compound (molding height, mold compound material properties), substrate thickness, TSV and die thickness effects.