Realistic stress representation in 2nd level interconnections of productive BGA components during drop test simulations

Virtual prototyping is able to speed-up the development cycle of new products if based on exact models. In case of dynamic mechanical loads like JEDEC drop tests of BGA modules, broken copper traces at the PCB side are more and more often observed to be the ultimate failure effects. Straightforward FEM simulations showed unrealistic high stress and strain results not matching with the experimentally gained characteristic lifetimes of productive BGA components. A comprehensive physical investigation of the failure formation during JEDEC drop tests has revealed the complex nature of the dynamic failure formation. In addition to the ultimate fracture of the copper trace, a flaw of the IMC layer on top of the PCB pad has been identified by 3-D X-ray tomography. Obviously, both failure mechanism are initiated during the consecutive drop events at different times propagating with different speeds. Both mechanisms are interacting with each other with no single mode alone dominating the failure evolution. Hence, FEM simulations have to account for both failure mechanisms in order to capture the ultimate copper trace stress realistically. Simulation results dramatically gained realism after including the IMC crack. The plastic copper trace strain is reduced by 80 % compared to an interconnection without IMC flaw. Now the plastic copper strain has reached realistic values indicating possible lifetimes as seen in the experiments. The overall routing effect of the PCB copper traces was investigated applying this new simulation methodology. The resulting strain map clearly indicates the routing direction, which is parallel to the short PCB edges and leaving the component as the most critical, which is in agreement with experimental observations. This very realistic 2^nd level interconnection model has been used to assess the lifetime of the investigated packages. A lifetime model was derived, which is able to predict the experimental number of cycles-to-failure of all - - three packages at different PCB positions with less than 25 % deviation. The results presented here set the ground for virtual prototyping, which also includes the BGA drop test endurance.