Title :
Near optimal embedding of binary tree architecture in VLSI
Author :
Youn, Hee Yong ; Singh, Adit D.
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Abstract :
An efficient scheme is presented for embedding a complete binary tree architecture in a two-dimensional array of processing elements. The scheme utilizes almost 100% of the processing elements in the array as actual computing elements, with small and asymptotically optimal propagation delay. The maximum edge length is optimal for trees with up to six levels. The scheme is compared with other designs proposed in the literature and shown to be significantly better
Keywords :
VLSI; computer architecture; trees (mathematics); VLSI; actual computing elements; asymptotically optimal propagation delay; binary tree architecture; maximum edge length; near optimal embedding; processing elements; two-dimensional array; Application software; Binary trees; Computer architecture; Dictionaries; Distributed computing; Parallel processing; Propagation delay; Silicon; Tiles; Very large scale integration;
Conference_Titel :
Distributed Computing Systems, 1988., 8th International Conference on
Conference_Location :
San Jose, CA
Print_ISBN :
0-8186-0865-X
DOI :
10.1109/DCS.1988.12503
