DocumentCode
2360347
Title
Design, fabrication and electrical characterization of TSV
Author
Zhang, L. ; Li, H.Y. ; Gao, S. ; Tan, C.S.
Author_Institution
Inst. of Microelectron., A*STAR (Agency for Sci., Technol. & Res.), Singapore, Singapore
fYear
2010
fDate
8-10 Dec. 2010
Firstpage
765
Lastpage
768
Abstract
In this paper, the electrical characteristics, such as CV and IV, of TSV embedded in grounded Si are presented. The aim is to understand the interaction between TSV and silicon substrate. Process developments of TSV with diameter of 5μm and height of 5-10μm are discussed in terms of DRIE Si via etching, isolation deposition, Cu ECP and Cu CMP.
Keywords
chemical mechanical polishing; elemental semiconductors; integrated circuit manufacture; silicon; sputter etching; three-dimensional integrated circuits; CMP; DRIE; ECP; TSV; chemical mechanical polishing; electrical characteristics; etching; isolation deposition; silicon substrate; size 5 mum to 10 mum; through-silicon-via; Cu CMP; Cu ECP; TSV; TSV etch; electrical characteristics; isolation deposition;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Packaging Technology Conference (EPTC), 2010 12th
Conference_Location
Singapore
Print_ISBN
978-1-4244-8560-4
Electronic_ISBN
978-1-4244-8561-1
Type
conf
DOI
10.1109/EPTC.2010.5702751
Filename
5702751
Link To Document