Resistance and inductance calculations of the tapered Through Silicon Vias

In this paper, formulas are proposed to calculate the parasitic resistance and inductance of the tapered Through Silicon Vias (TSVs). The expressions are developed as the functions of the via height, radius, and the distance between vias and the slope angle of the via walls. The comparison between the formula calculation and numerical electromagnetic simulation results shows that the maximum error is less than 3%, revealing the formulas have high accurate. These formulas provide an efficient way to optimize the impedance of the signal and power paths when using tapered TSVs in Three-Dimensional Integrated Circuits (3DICs).