Title : 
Fault tolerant circuits and probabilistically checkable proofs
         
        
            Author : 
Gál, Anna ; Szegedy, Mario
         
        
            Author_Institution : 
Dept. of Comput. Sci., Chicago Univ., IL, USA
         
        
        
        
        
        
            Abstract : 
We introduce a new model of fault tolerance for Boolean circuits. We consider synchronized circuits and we allow an adversary to choose a small constant fraction of the gates at each level of the circuit to be faulty. We require that even in the presence of such faults the circuit compute a “loose version” of the given function. We show that every symmetric function has a small (size O(n), depth O(log n)) fault tolerant circuit in this model. We also show a perhaps unexpected relation between our model and probabilistically checkable proofs
         
        
            Keywords : 
Boolean functions; computational complexity; fault tolerant computing; Boolean circuits; fault tolerant circuits; loose version; probabilistically checkable proofs; symmetric function; synchronized circuits; Boolean functions; Circuit faults; Computer science; Fault tolerance; Hardware; Redundancy;
         
        
        
        
            Conference_Titel : 
Structure in Complexity Theory Conference, 1995., Proceedings of Tenth Annual IEEE
         
        
            Conference_Location : 
Minneapolis, MN
         
        
        
            Print_ISBN : 
0-8186-7052-5
         
        
        
            DOI : 
10.1109/SCT.1995.514728