Analytical and TCAD-supported approach to evaluate intrinsic process variability in nanoscale MOSFETs

We propose an approach to evaluate the effect on threshold voltage variability due to line edge roughness (LER) and to surface roughness (SR) fully based on analytical modeling or supported by a limited number of TCAD simulations to perform parameter sensitivity analysis. We show that in the case of a 32 nm ultra-thin-body SOI MOSFET and a 22 nm double-gate MOSFET our approach is capable to reproduce with very good accuracy the results obtained through 3D atomistic statistical simulation at a small computational cost. We believe the proposed approach can be a powerful tool to understand the role of the main variability sources and to explore the device design parameter space.