Title :
Built-in fine resolution clipping with calibration technique for high-speed testing by using wireless testers
Author :
Cheng, Ching-Hwa ; Chung, Chen-I
Author_Institution :
Dept. of Electron. Eng., Feng-Chia Univ., Taichung, Taiwan
Abstract :
There are many test challenges generated from at-speed delay testing requirements. BIST circuit can help to solve traditionally slower ATE tester problems. In this paper, a double edge clipping technique is proposed for at-speed BIST testing. It differs from traditional circuit delay testing techniques by changing the clock rate using external ATE. This method uses lower-speed input clock frequency, then applies internal BIST circuit to adjust clock edges for circuit at-speed delay testing and speed binning. Test chips are fully validated. The postlayout simulations that show that the wide-range (26%~76%), fine-scale (16ps) duty cycle adjustment technique with high-precision (28ps) calibration circuit is effective for at-speed delay testing and performance binning.
Keywords :
automatic test equipment; built-in self test; integrated circuit layout; integrated circuit testing; system-on-chip; ATE tester problems; BIST circuit; at-speed BIST testing; at-speed delay testing requirements; built-in fine resolution clipping; calibration technique; circuit delay testing techniques; clock edges; clock rate; double-edge clipping technique; fine-scale duty cycle adjustment technique; high-precision calibration circuit; high-speed testing; lower-speed input clock frequency; postlayout simulations; speed binning; wireless testers; Built-in self-test; Circuit faults; Clocks; Delay; Integrated circuit modeling; Synchronization;
Conference_Titel :
Dependable Systems and Networks Workshops (DSN-W), 2011 IEEE/IFIP 41st International Conference on
Conference_Location :
Hong Kong
Print_ISBN :
978-1-4577-0374-4
Electronic_ISBN :
978-1-4577-0373-7
DOI :
10.1109/DSNW.2011.5958840
