Antifuse bitcell array design methodology driven by reliability study in 45nm

The proposed antifuse bitcell comprises a antifuse capacitor accessed through a thin-oxide cascode structure and is fully standard CMOS process compatible. The area of a reliable cell is in the range of 1 mum² in 45 nm core CMOS process. With respect to literature based on 0.18 mum CMOS process, the development in advanced CMOS technologies (45 nm and beyond) leads to stringent reliability requirement. Particularly, the cas-code must ensure a good trade-off between reliability and density. An original design method based on experimental reliability study is presented. A primary 8 kb matrix has been fabricated in 45 nm standard CMOS process. Reliability is studied for stand-alone bitcells in every configuration of array in order to define the optimal final size of the memory cut. Reliability analysis and design results indicate that a 64 kb reliable OTP matrix can be fabricated in one cut in the worst case of programming mode which is far beyond the previously published fuse matrices. A 64 kb memory cut addresses the needs of numerous applications.